Analog & Mixed-Signal IC Layout
More than 50 successful tapeouts across technologies from 14nm to 350nm. Our layout team brings over two decades of hands-on experience in full custom physical design, top-level integration, and silicon sign-off.
Layout Capabilities
End-to-end physical design from block-level layout to top-level integration and tapeout sign-off.
Block-Level Layout
Full custom analog and mixed-signal block layout with precision matching structures.
- Voltage regulators, bandgaps, V2I converters
- ADC/DAC, sigma-delta modulators, PLLs
- LNA, TIA, PGA, continuous-time filters
- Charge pumps, oscillators, I/O buffers
- Current DAC, imaging sensor amplifiers
- ESD protection structures (2.5kV to 16kV)
Top-Level Integration
Chip-level floorplanning, power/ground distribution, and full integration of analog, digital, and RF cores.
- Chip area estimation and floorplanning
- Power & ground star distribution planning
- Multi-domain supply management (16+ domains)
- Signal path routing and shielding
- I/O ring design and custom I/O interfaces
- Digital block insertion and P&R validation
Verification & Sign-off
Rigorous physical verification and tapeout preparation for first-time-right silicon.
- DRC, LVS, Antenna, ERC checks
- Parasitic extraction (LPE/PEX/QRC)
- IR drop analysis and EMIR sign-off
- Post-layout optimization
- GDSII delivery and reticle assembly
- Bonding diagram preparation
Layout-Aware Design Support
Close collaboration between schematic and layout teams to ensure design intent is preserved.
- Pre-layout area estimation and feasibility
- Layout-driven design methodology
- Cross-talk and signal integrity analysis
- Flip-chip bump alignment verification
- Design kit evaluation and feedback
- CAD flow setup and automation (SKILL, Tcl)
Application Domains
Proven layout experience across safety-critical and high-performance application areas.
Power Management (PMIC)
Block layout for TX drivers, charge pumps, gate drivers, and full PMIC top-level integration across BCD and HV processes.
Automotive Sensing
Mixed-signal layouts for wireless transceivers, radar ADCs, Hall-effect sensor AFEs, MEMS pressure sensors, and magnetic switches.
Biosensors & Medical
Ultra-low noise analog front-ends for in-memory compute platforms, ultrasound receivers, and nanopore DNA sequencing ASICs including custom sensor reticle mask sets.
RF & Communication
UWB transceiver layouts, multiband frequency synthesizers, LVDS pads, and high-speed serial I/O interfaces up to several GHz.
Structured ASIC & Digital
Configurable I/O libraries, clock tree structures for 32+ domains with zero skew, and physical verification for designs with up to 10 million logic gates.
High-Voltage & Energy
Isolated gate driver layouts for power management in automotive battery chargers, programmable high-voltage drivers (up to +/-40V), and energy harvesting ICs.
Foundry & Process Coverage
Hands-on tapeout experience across a comprehensive range of foundries and process nodes.
| Foundry | Process Nodes |
|---|---|
| TSMC | 180nm, 150nm, 130nm, 130nm BCD, 90nm, 65nm, 40nm, 28nm |
| Samsung | 14nm |
| IBM | 180nm, 40nm, 22nm |
| GlobalFoundries | 90nm, 65nm, 22nm |
| UMC | 180nm, 150nm, 130nm |
| Tower Jazz | PD-SOI 180nm, TS 180 PM |
| X-Fab | 180nm HV |
| OnSemi | 180nm BCD I4T |
| AMS | 350nm |
| Infineon | 320nm, 250nm, 180nm, BiCMOS |
| STMicroelectronics | 130nm, 90nm |
| Dongbu | 180nm, 130nm |
| Siltera | 180nm |
| TI | LBC9 |
EDA Tool Proficiency
Deep expertise across industry-standard design and verification platforms.
Cadence
- Virtuoso Layout Editor (Virtuoso XL)
- Assura DRC/LVS/LPE
- PVS physical verification
- Spectre RF simulator
- Virtuoso AMS Design Flow
Siemens EDA (Mentor)
- Calibre DRC & LVS
- xCalibre parasitic extraction
Synopsys
- Custom Compiler for analog layout
- IC Validator (ICV) DRC/LVS/LPE
Automation & Scripting
- SKILL (Cadence scripting)
- Tcl & Shell scripting
- Verilog-A/AMS
Representative Layout Projects
A selection of completed layout engagements across diverse applications and process nodes.
PMIC TX Driver IP
Block layout for high-current TX driver in TSMC 130nm BCD and OnSemi 180nm BCD I4T processes.
Isolated Gate Driver
Layout for isolated gate driver targeting automotive battery charger power management in X-Fab 180nm HV.
PD-SOI Full Chip Integration
Block layout for decoders, charge pumps, switch drivers, I/Os and ESD. Top-level integration of digital, analog, and RF cores in Tower Jazz PD-SOI 180nm.
Nanopore DNA Sequencing ASIC
Multiple test chip versions in TSMC 180nm and 40nm: all analog and mixed-signal block layouts, top-level integration, sign-off, and custom nanopore sensor reticle mask sets.
HV Charge Pump & Sigma-Delta ADC
Block layout for HV charge pump, sigma-delta modulator (ADC), integrator, and PLL. Full top-level integration and sign-off in AMS 350nm.
Block Layout Fixes & Sign-off (14nm–40nm)
Block layout fixes with block and top-level physical verification and sign-off in Samsung 14nm, IBM 40nm and 22nm.
AFE for In-Memory Compute
Transimpedance amplifier, programmable-gain amplifier, voltage buffers, and MUXes. Input-referred noise < 1nArms over wide bandwidth. GF 22nm.
Ultrasound Receiver AFE
Low-noise amplifier with programmable gain and bandwidth. Input-referred noise < 1nArms over several MHz. X-Fab 180nm.
Multipurpose MEMS Drivers
System topology, PGA, monitoring/control, LDOs, and drivers. Programmable drive voltage +/-40V from 5V supply. X-Fab 180nm HV.
Automotive Radar & Sensor ICs
Mixed-signal layouts for radar (16-bit ADC, delay lines, multiplexers), wireless transceivers, magnetic switches, and MEMS pressure sensors in Infineon BiCMOS.
Ultra-Low Power RTC Regulators
Ultra-low power LDO with fast transient response and high-accuracy comparators. Bandgap + regulator < 5μA quiescent current. TSMC 28nm.
UWB Transceiver Frequency Synthesizer
Programmable gain, channel filter, and multiband frequency synthesizer. Output from hundreds of MHz to several GHz. TSMC 90nm and 65nm.
Engagement Model
Flexible and transparent collaboration tailored to your project requirements.
Your Infrastructure
We work exclusively on your tools and work areas, using your email and platforms for all project communication.
Internal Sign-off
All deliverables are reviewed and signed off by our IC technical lead before handover. Own team management and schematic-layout interface.
Full Documentation
Weekly progress reports, scheduled design reviews, and technical documentation via customer platforms (e.g., Jama).
Time & Materials
Flexible T&M engagement for projects with evolving requirements. All IP developed during the project is retained by the customer.
European-Based Layout Team
Our analog layout team is based in Europe, offering seamless nearshore collaboration within EU time zones and legal frameworks.
The European Advantage
Working within the EU semiconductor corridor means your IP is protected by the world's most stringent legal frameworks. Our team operates in your time zone (GMT+2), on your infrastructure, following your design flows — eliminating the risks associated with far-shore outsourcing while delivering world-class silicon results.
Ready to discuss your layout project?
Whether you need block-level layout, full chip integration, or tapeout sign-off support, our experienced team is ready to deliver.
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